Beschreibung
Our client based in Austria, Graz are seeking an engineer to join their verification team.You will be responsible for verification of RTL at block and SOC level.
Debug and maintain test code to meet exact standards.
60% Remote after an initial period of 2 months on site
Skills/Experience -
Experience working with Hardware design
RTL - Verligo/SystemVerilog/VHDL
OOD - Experience with writing code in embedded C/Java would be a bonus.
Experience in the use of EDA tools for IC development, simulation and debug
Many thanks,
Michael