Beschreibung
My Paris based client is urgently searching for 2 Digital ASIC Backend Engineers to come on board ASAP for a 6 month contract.We're looking for candidates with a solid understanding of digital architecture to drive physical design implementation aspects whilst working closely with the RTL design team - any candidates who have worked on projects with multiple clock domains with clock frequency up to 2GHz under clock synchronization constraints will be at an advantage.
Requirements:
- Responsible for implementation from RTL to GDSII to of a complex ASIC in advanced CMOS processes
- Manage floorplan, pin placement and block top level assembly
- Perform Formal Proof, Place and Route and STA
- Experience with 40nm Global Foundry technology