ASIC Design Engineer - €75 p/h - 12 Month Project

Beschreibung

ASIC Design Engineer - Leuven - 12 Month Contract - €75 p/h - ASAP Start - Some Remote Available

Our client is in the process of curating an advanced robotic arm with the aim of drastically increasing efficiency in the field of cardiac surgery.

For this, we are searching for a seasoned ASIC Design Engineer who has used either Cadence or Synopsys in a professional environment as well has having played a key part in both the back end and front end design.

This project will largely revolve around the generation and verification of the RTL and Netlist views of touch controller ICs in deep submicron CMOS processes, 55nm and beyond. Further to this, you will be expected to ensure device integration inclusive of analogue, digital IPs, memories, IOs and passives.

Requirements:

• Expertise in VHDL and Verilog RTL Languages
• Experience of Mixed Signal design - particularly with DAC, ADC or PLL
• Working knowledge of Synopsis and Cadence tool suites and Matlab
• Good scripting skills (perl, sed, awk, tcl, C)