Beschreibung
Hiring for Digital IP Verification Engineer with one of our esteemed Clients.
Location: Villach, Austria
Contract can extend long term.
Job Responsibilities/Work packages:
- Verification of digital IP's written in VHDL/Verilog with SystemVerilog and C
- Definition and implementation of verification concepts with SystemVerilog/UVM
- Generation of randomized testcases
- Setup regression flows
- Write assertion
- Write scoreboards, monitors
- Extension of available testcases written in SV and C
Required:
- Specialist in System Verilog and UVM
- Very experienced in C
- Very experienced in VHDL/Verilog
Desired:
- Make file generation
- Scripting language Shell/csh/Perl