16.09.2026 aktualisiert
100 % verfügbar
Senior Analog Layout / ESD Engineer
Yerevan, Armenien
Nur Remote
MS Electronic Engineering, Yerevan State Engineering University (Honors), 1995-1997Über mich
I build ESD protection solutions for difference nodes, layout verifications, schematic and post-layout characterizations. Specializing HBM/CDM schematic and post-layout simulation, current-density, DRC/LVS/ERC/PERC signoff. Developed and optimized protection cells, resolving physical verification.
Skills
DebuggingHalbleiterbauelementeSimulationenDesign Verification Test
Analog / Custom IC Layout
Expertise in device-level layout, matching, symmetry-aware placement, area-constrained layout, clamp/trigger/diode cells, core and I/O protection across advanced process nodes including GlobalFoundries 22 nm, 14 nm, 12 nm and TSMC/Samsung 2 nm, 3 nm, 4 nm, 5 nm, and 7 nm technologies.
ESD Protection Cell Development
Development and physical implementation of custom ESD protection cells, including clamp, trigger, and diode architectures across core and I/O domains, as well as HBM/CDM simulation, characterization, and functional validation of ESD-related cells.
Physical Verification
Execution and debugging of DRC, LVS, ERC, and PERC verification flows using ICV and Calibre tools, including signoff support and resolution of complex physical-verification issues in custom cells and foundry libraries.
Reliability and Electrical Robustness
Analysis of electromigration, current density, and power distribution, including XARA current-density checks and SAE HBM/CDM simulations to ensure electrical robustness and manufacturability.
Foundry Library Development
Support of multi-node foundry-library development and verification, translating reliability and ESD requirements into manufacturable physical layouts and integrating ESD tie-slow and protection cells into foundry libraries.
Validation and Test Methodology
Development and execution of validation methodologies and test plans for high-speed interface IP, including USB 2.0/3.0, DDR, SSP, and UPx solutions, as well as functional and performance result analysis.
Database and GIS Development
Design of drainage-system databases and GIS/AutoCAD models for environmental and hydrological systems, as well as development of Access-based trademark/patent application databases.
Software Engineering and Data Processing
Database development, energy-system modeling, data processing and analysis, cost-recovery studies, and technical reporting in software engineering roles.
Expertise in device-level layout, matching, symmetry-aware placement, area-constrained layout, clamp/trigger/diode cells, core and I/O protection across advanced process nodes including GlobalFoundries 22 nm, 14 nm, 12 nm and TSMC/Samsung 2 nm, 3 nm, 4 nm, 5 nm, and 7 nm technologies.
ESD Protection Cell Development
Development and physical implementation of custom ESD protection cells, including clamp, trigger, and diode architectures across core and I/O domains, as well as HBM/CDM simulation, characterization, and functional validation of ESD-related cells.
Physical Verification
Execution and debugging of DRC, LVS, ERC, and PERC verification flows using ICV and Calibre tools, including signoff support and resolution of complex physical-verification issues in custom cells and foundry libraries.
Reliability and Electrical Robustness
Analysis of electromigration, current density, and power distribution, including XARA current-density checks and SAE HBM/CDM simulations to ensure electrical robustness and manufacturability.
Foundry Library Development
Support of multi-node foundry-library development and verification, translating reliability and ESD requirements into manufacturable physical layouts and integrating ESD tie-slow and protection cells into foundry libraries.
Validation and Test Methodology
Development and execution of validation methodologies and test plans for high-speed interface IP, including USB 2.0/3.0, DDR, SSP, and UPx solutions, as well as functional and performance result analysis.
Database and GIS Development
Design of drainage-system databases and GIS/AutoCAD models for environmental and hydrological systems, as well as development of Access-based trademark/patent application databases.
Software Engineering and Data Processing
Database development, energy-system modeling, data processing and analysis, cost-recovery studies, and technical reporting in software engineering roles.
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2026
Sprachen
EnglishverhandlungssicherRussianverhandlungssicher
Projekthistorie
Led development and physical implementation of custom ESD protection cells including clamp, trigger, and diode architectures across core and I/O domains. Performed advanced-node custom layout work across GlobalFoundries 22 nm, 14 nm, 12 nm and TSMC/Samsung 2 nm, 3 nm, 4 nm, 5 nm, and 7 nm technologies. Optimized cell architecture and layout for tight area targets. Ran and debugged DRC, LVS, and ERC verification flows. Conducted HBM/CDM simulation and characterization, current-density analysis, and validation of clamp/trigger functionality. Created layout guidelines and supported foundry ESD library implementation.
Performed analog/custom layout design with emphasis on device matching, placement, routing constraints, and compact cell implementation. Solved layout challenges involving device matching, electromigration, power distribution, current density, and strict circuit-area restrictions. Ran, debugged, and closed ICV/Calibre DRC, ERC, LVS, and PERC verification issues. Developed and debugged ESD tie-slow and protection cells and supported their integration into foundry libraries. Worked with R&D engineers on XARA current-density checks, SAE HBM/CDM simulations, and functional validation of ESD-related cells. Supported multi-node library development and verification.
Developed and executed validation methodologies and test plans for high-speed interface IP, including USB 2.0/3.0, DDR, SSP, and UPx solutions. Analyzed functional and performance results, identified issues, and collaborated with development teams on corrective actions, integration, and release qualification. Improved testing strategies, quality processes, and release workflows across the product lifecycle.