19.10.2026 aktualisiert
Premiumkunde
100 % verfügbarEmbedded Systems Architect · Firmware · FPGA · Functional Safety · Bring-up · RTOS · Secure Boot
Steyregg, Österreich
Weltweit
Über mich
I work on complex embedded systems in early project phases and in critical situations where systems need structure, technical direction, or recovery. Remote-first with my own lab, on-site whenever needed. Contracts through KS Metrology Solutions GmbH.
Skills
C (Programmiersprache)ARM ArchitekturC++GerätetreiberEmbedded C++Embedded SystemsEmbedded BetriebssystemeEmbedded SoftwareEthernetEthercatFirmwareFPGAFunktionale SicherheitIso 26262Python
I bring nearly two decades of embedded systems and HW/SW integration at Infineon and Bosch: firmware architecture for automotive radar SoCs, first-silicon bring-up, and software safety mechanisms up to ASIL C. At KS Metrology Solutions, which I co-founded, I build the complete digital platform myself, from system architecture and FPGA logic to firmware, HMI and the test framework.
Selected results
- Technical lead for the firmware of an automotive radar IC assessed to ISO 26262 ASIL C by exida and in series production; the safety concept ran entirely in software on a core without dedicated safety hardware
- First silicon fully functional by midday of day one, on Infineon's first complex radar IC. I proposed the fully scripted approach and owned the tooling, the scripts and their review; recognized with a performance bonus.
- Firmware organization built from two people to ~25 engineers across six countries, ASIL B and ASPICE Level 2 readiness confirmed in internal pre-assessments
- Instrument firmware platform taken to a functional system demonstrator in 18 months: RTOS-based firmware on STM32N6, USB device and host plus Ethernet interfaces, touch and web HMI, secure boot with A/B updates, portable across three MCUs, backed by 3,000+ unit tests
- Cut the runtime of an already NEON-optimized LiDAR signal processing pipeline on ARM Cortex-A by about 50 %, bringing it within the product's timing budget
Typical engagement scenarios
- Systems exhibit unexpected behavior that is difficult to debug
- A new board, a prototype or first silicon does not behave
- A project is stalled due to technical complexity or deadline pressure
- Alignment between hardware, FPGA, and firmware teams is missing
- An MCU or a key part goes end-of-life and the firmware has to move to new silicon without breaking the product
- A critical path misses its throughput or latency target and nobody knows where the time goes
Co-inventor on four granted patents in automotive radar ICs (as Georg Krebelder).
Technologies: C/C++, Python, VHDL · STM32, ARM Cortex-M and Cortex-A, NEON · Xilinx, Lattice · RTOS (ThreadX), secure boot, OTA updates · PCIe, USB, Ethernet, EtherCAT · SCPI, HiSLIP, VXI-11 · HMI (LVGL, web)
Safety & process: Functional safety (ISO 26262, ASIL B/C), MISRA C, ASPICE, WCET analysis, HIL testing, first-silicon bring-up
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2025
Sprachen
DeutschMutterspracheEnglischverhandlungssicher
Projekthistorie
Own product development: precision power supply with battery simulation and high-speed data acquisition. Responsible for the complete digital platform: architecture, FPGA, firmware, HMI and test.
- System and firmware architecture with HW/SW co-design: MCU selection, interfaces, boot and update concept, deterministic timing in the FPGA
- Target-independent firmware API with a board-support layer for Microchip SAM E70, STM32U5 and STM32N6; port to the STM32N6 in three months, replacing two MCUs with one
- FPGA logic: hardware sequencer for ADC/DAC timing and control of the analog front end
- SCPI communication layer over USB-TMC, USB-CDC, HiSLIP, VXI-11, raw TCP and WebSockets
- Secure boot; encrypted and signed A/B updates over the network with rollback; in-system FPGA update with SPI recovery for blank MachXO2 devices
- Touch HMI with LVGL and HTML5 web interface; test framework with GoogleTest unit tests and pytest/PyVISA end-to-end tests, using AI-assisted test generation
Result: Functional system demonstrator after 18 months; 25 MB/s via USB-TMC, 37 MB/s via HiSLIP, first GUI frame in under 250 ms after ROM bootloader handover, 3,000+ unit tests.
Technologies: C, C++, Python, VHDL, STM32N6, STM32U5, Microchip SAM E70, ARM Cortex-M7/M33/M55, Lattice MachXO2, ThreadX, FileX, lwIP, USB device and host, Ethernet, TCP/IP, SCPI, HiSLIP, VXI-11, IEEE 1588 PTP, secure boot, A/B firmware updates, LVGL, GoogleTest, pytest, PyVISA
Radar SoC for ADAS applications. Responsible for the firmware program within a project of ~100 engineers: series, validation, production test and customer demo firmware, plus lab tooling and board support.
- Build-up of the distributed firmware organization from two people to ~25 engineers in Austria, Germany, France, Ireland, Bulgaria and the Netherlands, plus contractors: roles, responsibilities, development structure; final six months on site in Sofia
- System-level firmware architecture; definition of a dedicated housekeeping CPU in the SoC with a stable firmware API towards the customer software
- Delivery process: Scrum with sprint planning and dailies, 3-week release cycles with management release reviews, firmware Jira project with change workflow
- Initiation of a HIL validation environment with automated radar scenarios and pass/fail evaluation for every release
- Organization of the firmware ecosystem for first-silicon bring-up with Python tooling, register access abstraction and verification integration; coordination of the lab bring-up across firmware, hardware and verification
- ASIL B firmware development system and ASPICE process in daily practice; technical alignment with the customer on scope, responsibilities, timelines and deliverables
Result: ASIL B and ASPICE Level 2 readiness confirmed in internal pre-assessments.
Technologies: MISRA C, HIL testing, release management, requirements engineering, IBM DOORS, Helix QAC, Jira, Confluence, Jenkins
Solid-state LiDAR modules based on the LeddarEngine: LeddarCore SoC generations LCA2 and LCA3 with the LeddarSP signal processing software on a Renesas R-Car host processor. Member of the Linz architecture team, working with the headquarters in Quebec City.
- Runtime optimization of the critical LeddarSP signal processing stages on ARM Cortex-A with NEON, at instruction level in the QEMU simulator and backed by regression tests
- Scaling analysis for the next generation together with the system architect: compute time grows quadratically to cubically with pixel count
- HW/SW partitioning: assessment of each signal processing algorithm for software, FPGA, or simplification
- Evaluation of CPU, GPU and FPGA platforms; preparation of the platform decision for Xilinx Zynq
Result: Runtime of the critical stages reduced by about 50 % on already NEON-optimized code; the current generation met its timing budget.
Technologies: C, C++, ARM assembly, ARM Cortex-A, ARM NEON, SIMD optimization, HW/SW partitioning, regression testing, QEMU