Beschreibung
Role: x2 Verification engineers
Location: Austria
Description:
Our client are seeking X2 contract verification engineers within the UVM space for system level verification using tools such as System Verilog, to work on a project for test sequence implementation.
This large semiconductor company are a leader in their field.
The project will last from 3 months to 12 months
Skills
UVM, system Verilog
Test bench sequence simulation
system Verilog
ASIC
Send me a CV ASAP
Thanks
Jack