Engineer High Voltage Design

Vertragsart:
Vor Ort
Start:
ASAP
Dauer:
6months +
Von:
MBA - Muenchen
Ort:
Steiermark
Eingestellt:
07.11.2012
Land:
flag_no Österreich
Projekt-ID:
444090

Warning
Dieses Projekt ist archiviert und leider nicht (mehr) aktiv.
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For our client in Austria we are currently looking for:

Engineer High Voltage Design (m/f)

Education/Experience:

  • University or FH degree in Electronics or related
  • Understanding of key analog building blocks
  • Understanding of Lab and Test constraints on analog design
  • Understanding of design and layout, preferably already in HV-CMOS processes (50V)
  • Experience on power management blocks as eg dcdc, regulators, is a plus
  • Experience with Cadence design tools
  • Minimum 2 years experience in analog design

Job description/tasks and responsibilities:

  • Design, simulation and verification of analog HV blocks
  • Generation of Verilog-A models for self designed blocks
  • Model simulation of Sub-Blocks
  • Performing design reviews
  • Supervision of layout generation
  • Guidance of Lab measurements

Start: ASAP
Location: Graz
Duration: Project or Permanent position

Looking forward to hearing from you soon!

Michael Bailey International is acting as an Employment Business in relation to this vacancy.