Beschreibung
My client based in Hamburg is looking for an experienced FPGA design engineer on a 6 month basis. The current project is not for the faint hearted and offers a real challenge to successful applicants.The role/ responsibilities:
• Decomposition of requirements into an architecture design and document the chosen design whilst describing any trade-offs performed.
• Detailed RTL design in VHDL.
• Verification of the RTL design and documenting the verification that was performed.
• Gate level implementation of the design including synthesis, placement and static timing analysis.
• Support integration of the FPGA into the target hardware.
• Ensure that all FPGA designs are developed in accordance with the company design process.
Needs:
• 10 years of FPGA experience;
• Verilog for design and verification;
• Low latency design;
• Recent experience of Xilinx / Altera FPGAs;
• Design and implementation of automated verification testbenches;
• Mathematical / DSP implementation in FPGA. Nice to have:
• SystemVerilog for design and verification
• Network / packet processing experience;Financial market data processing; &
• C/C++ programming language.