Beschreibung
Digital IP Verification Engineer
Required urgently for a 6 month extendable contract based in Austria.
The required experience is as follows:
Verification of digital IP's written in VHDL/Verilog with SystemVerilog and C
Definition and implementation of verification concepts with SystemVerilog/UVM
Generation of randomized testcases
Setup regression flows
Write assertion
Write scoreboards, monitors
Extension of available testcases written in SV and C
Requested skill set/experience level:
5+ years experience
Specialist in System Verilog and UVM
Very experienced in C
Very experienced in VHDL/Verilog
If you are interested, please send your CV over to (see below)