Beschreibung
My Customer based in Villach, Austria currently require Digital IP Verification Engineers, this a contract role.
Location: Villach, Austria
Duration: 6 - 12 Months
Start: April 1, 2016
Rate: Open to discuss
Tasks/Job Responsibilities:
- Verification of digital IP's written in VHDL/Verilog with SystemVerilog and C
- Definition and implementation of verification concepts with SystemVerilog/UVM
- Generation of randomized testcases
- Setup regression flows
- Write assertion
- Write scoreboards, monitors
- Extension of available testcases written in SV and C
Requested skill set/experience level:
- >5 year experience
Required skills:
- Specialist in System Verilog and UVM
- Very experienced in C
- Very experienced in VHDL/Verilog
Desired Skills:
- Make file generation
- Scripting language Shell/csh/Perl
Applicants for this role must be eligible to live and work in the EU, please submit your CV now for consideration.