Profilbild von Anonymes Profil, FPGA/ASIC/Embedded-Designer
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Letztes Update: 06.09.2022

FPGA/ASIC/Embedded-Designer

Abschluss: B. Mus, B. Sc. (Computer Engineering, 4th semester)
Stunden-/Tagessatz: anzeigen
Sprachkenntnisse: deutsch (Muttersprache) | englisch (verhandlungssicher)

Skills

I'm a german Computer Engineering student in 4th semester. I have extensive experience in FPGA design and embedded systems. Currently working for FAIR (Facility for Antiproton and Ion Research) and involved in an FPGA/ASIC-project at Leibniz University Hannover. Several years of experience in low-level embedded systems using C (ARM Cortex M, ESP32 with ESP-IDF, Atmel AVR, TI wireless chips). 1 year of work experience in the IoT industry.
I have 4 years of experience writing RTL code in both VHDL and SystemVerilog, testing and verification using testbenches and UVM. Focus on FPGA implementations. I have all the equipment needed to prototype any kind of electronic circuit needed (soldering, microscope, oscilloscopes, digital analyzers, laser cutter, lots of different FPGAs, microcontrollers, electronic parts). I love beautiful and clear HDL code.

Projekthistorie

02/2022 - bis jetzt
Software Developer
FAIR (Facility for Antiproton and Ion Research) (Internet und Informationstechnologie, 1000-5000 Mitarbeiter)

Designing tools for coordination of multiple CAD models and management of the interaction of different construction companies.
I'm working in a team of 10 experts using Jira, git and agile principles.

11/2021 - bis jetzt
Embedded Systems and IoT designer
SigmaHeat GmbH (Energie, Wasser und Umwelt, 10-50 Mitarbeiter)

Development of Hard- and Software for smart metering.
Mostly low-level/bare-metal-programming in C, sometimes using FreeRTOS or TI-RTOS.
Have designed PCBs with EAGLE.

03/2021 - bis jetzt
FPGA/ASIC designer
Leibniz Universität Hannover (Sonstiges, 10-50 Mitarbeiter)

Testing, verification, making suggestions for improvements and implementation of a complex VHDL design for accelerating neural nettworks on a Xilinx FPGA.
Writing testbenches, behavioral and post-syth-simulations, physical implementation.

Reisebereitschaft

Weltweit verfügbar
Ideally I want to work remotely 10-20 hours/week in a project
Profilbild von Anonymes Profil, FPGA/ASIC/Embedded-Designer FPGA/ASIC/Embedded-Designer
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