Consultant Hardware/Software Development
Siemens CVC
Skills
C++, C, OOA/OOD, Requirements Engineering, Testing, Avalon, AMBA, AHB, APB, AXI, SPI, I2C, NIOS, ARM Cortex-A9, TriCore, Xtensa, PIC, C/C++, VHDL, Verilog, SystemC, Python, Perl, tcl, Ada95, Javascript, OWL, STL, QT, Digital Design Tools, Quartus, Libero, ISE, Vivado, Questa, ModelSim, Design Compiler, RTL, Compiler, SoC Encounter, Apollo, Prime Time, Formality, NC-Verilog, Tetramax, HSPICE, Gnu, Make, Altium Designer, Eagle, Compilers, IDEs, gcc, Eclipse, Microsoft Visual Studio, gnu-Make, JBuilder, ObjectAda, gdb, Universal Debug Engine, FPGA, firmware, LTE, ASIC, Back-End, SPICE, LIDAR, Libero 12.1, Linux, XILIX ISE, SCPI, Ethernet, Django, OAuth 2.0, signal processing, system testing, scripting framework, interface, Quartus tcl interface, Perl scripting, metadata, Python scripting, Interfaces, html, web-service, SOAP, COM, communication protocol, DSP, coding, DSP algorithm, Spyglass, Tensilica, FFT, C++/SystemC code, Programming, Scrum, QT Libraries, SoC-Encounter, NC-Sim, X-Graph, CMMs, sensor, MS-Project, PCB, TCP/IP, Logic, TCP/IP Interface, Altera, SoPC Builder, SDH, SONET, macros, ATPG, algorithms, Mapper, DS3, OPUS/NEXUS tools, IKOS, OPUS, NEXUS, scripting, parameterized, CAN-Bus, microcontroller, GUI, Java, CORBA, C++ Programmer, image processing, Opto-Mechatronic Systems, Urdu
Projekthistorie
02/2017
-
08/2018
Worked on development of EGSE (Electronic Ground Support Equipment)
at Space department of Siemens Convergence Creators GmbH in Vienna.
at Space department of Siemens Convergence Creators GmbH in Vienna.
02/2017
-
08/2018
Consultant Hardware/Software Development
Siemens (later Atos) Convergence Creators
Role: Working in the "Space" department on development of a Solar Array
Simulator, used in verification and test of Satellite's power system.
Technologies: VHDL, XILIX ISE, Modelsim, Altium Designer, JavaScript, SCPI, Python
Simulator, used in verification and test of Satellite's power system.
Technologies: VHDL, XILIX ISE, Modelsim, Altium Designer, JavaScript, SCPI, Python
03/2017
-
06/2017
Consultant
Hybridserver Tec GmbH
Worked on FPGA-development of a new concept of high speed servers.
03/2017
-
06/2017
Consultant FPGA-Development
Hybridserver Tec GmbH
Role: Worked on the development of a Gigabit Ethernet Switch as a part of a
new concept of next generation high speed servers. It was used as a
packet switch between a 40 Gb Ethernet on one side and 6
microprocessor cores, each connected with a 10 Gb Ethernet on the other
side.
Technologies: VHDL, Xilinx Vivado, Questa, AMBA AXI4-Stream, AXI-Lite, Python
new concept of next generation high speed servers. It was used as a
packet switch between a 40 Gb Ethernet on one side and 6
microprocessor cores, each connected with a 10 Gb Ethernet on the other
side.
Technologies: VHDL, Xilinx Vivado, Questa, AMBA AXI4-Stream, AXI-Lite, Python
10/2016
-
01/2017
Consultant Embedded Software Development
IExergy GmbH
Worked on firmware development for smart-home products.
10/2016
-
01/2017
Consultant for Embedded Software Development
IExergy GmbH
Role: Worked on further development of their product WiButler. Worked on
smart-home "skill" development for Amazon-Echo.
Technologies: Python, Django, JavaScript, OAuth 2.0
smart-home "skill" development for Amazon-Echo.
Technologies: Python, Django, JavaScript, OAuth 2.0
09/2013
-
09/2016
Consultant
SEW Eurodrive GmbH & Co. KG
Worked in the R&D Department on development and
verification/validation of a new generation of frequency converters.
verification/validation of a new generation of frequency converters.
09/2013
-
09/2016
R&D Consultant for Verification and Validation
SEW-Eurodrive GmbH & Co KG
Role: * Worked on test and validation of a new generation of inverters
(frequency converters). Inspected all its existing requirements for
sanity and redundancy. Wrote requirements for "undefined" parts
of the system keeping international norms (like IEC 61131) in
consideration. Suggested tests for those requirements. Carried
them out and documented each test.
* Worked specifically on "encoder signal processing" and binary
inputs/outputs by writing requirements, suggesting tests for those
requirements and carrying out and documenting those tests
during and after the development.
* Developed and verified an SPI-based "diagnosis interface" (using
VHDL) for inverters to get and display the key parameters of
inverter during its operation.
* Introduced regression tests for hardware-software system testing.
Developed a scripting framework for regression tests based on
UDEDebugger's COM interface, Quartus tcl interface, Perl scripting
and Make files.
* Most important : Introduced IP-XACT (metadata) based system
design and documentation flow. Evaluated different off-the-shelf
IPXACT tools on behalf of SEW but the developers were not happy
with their end results. I ended up writing my own tool using
extensive Python scripting. Both hardware and firmware
development teams have readily accepted it. This tool takes IP-
XACT description as input and generates Hardware Abstraction
Layer (HAL) in C++, Register Interfaces in VHDL and html
documentation of all memory mapped register. This tool has
eliminated a major cause of faults in the design flow.
* Worked on a system-tester based on a Cyclone-V board with
Cortex-A9 cores and μClinux. Tested the board by writing simple
drivers. Developed a web-service (SOAP) based interface between
PC and the test board.
Technologies Python, C++, RE, VHDL, Quartus, Modelsim, μClinux, Cyclone-V, Arm
Cortex-A9, IP-XACT, oscilloscope, logic analyzer, TriCore UDE-Debugger,
COM, SOAP
(frequency converters). Inspected all its existing requirements for
sanity and redundancy. Wrote requirements for "undefined" parts
of the system keeping international norms (like IEC 61131) in
consideration. Suggested tests for those requirements. Carried
them out and documented each test.
* Worked specifically on "encoder signal processing" and binary
inputs/outputs by writing requirements, suggesting tests for those
requirements and carrying out and documenting those tests
during and after the development.
* Developed and verified an SPI-based "diagnosis interface" (using
VHDL) for inverters to get and display the key parameters of
inverter during its operation.
* Introduced regression tests for hardware-software system testing.
Developed a scripting framework for regression tests based on
UDEDebugger's COM interface, Quartus tcl interface, Perl scripting
and Make files.
* Most important : Introduced IP-XACT (metadata) based system
design and documentation flow. Evaluated different off-the-shelf
IPXACT tools on behalf of SEW but the developers were not happy
with their end results. I ended up writing my own tool using
extensive Python scripting. Both hardware and firmware
development teams have readily accepted it. This tool takes IP-
XACT description as input and generates Hardware Abstraction
Layer (HAL) in C++, Register Interfaces in VHDL and html
documentation of all memory mapped register. This tool has
eliminated a major cause of faults in the design flow.
* Worked on a system-tester based on a Cyclone-V board with
Cortex-A9 cores and μClinux. Tested the board by writing simple
drivers. Developed a web-service (SOAP) based interface between
PC and the test board.
Technologies Python, C++, RE, VHDL, Quartus, Modelsim, μClinux, Cyclone-V, Arm
Cortex-A9, IP-XACT, oscilloscope, logic analyzer, TriCore UDE-Debugger,
COM, SOAP
06/2012
-
06/2013
R&D Consultant
Robert Bosch GmbH
Corporate Research department of Robert Bosch GmbH works on design
and development of products of strategic importance. I worked on
development and verification of Layers 2 and 3 of a new field bus.
and development of products of strategic importance. I worked on
development and verification of Layers 2 and 3 of a new field bus.
06/2012
-
06/2013
R&D Consultant
Robert Bosch GmbH
Role: Design, development and verification of a new field bus. The design was
implemented on an FPGA development board. My responsibilities
included development and verification of Layer 2 and 3 of the devised
communication protocol of this new Ethernet-compatible field-bus
Technologies: C, C++, NIOS, Perl, DSP, Lab instruments like oscilloscope and logic
analyzer.
implemented on an FPGA development board. My responsibilities
included development and verification of Layer 2 and 3 of the devised
communication protocol of this new Ethernet-compatible field-bus
Technologies: C, C++, NIOS, Perl, DSP, Lab instruments like oscilloscope and logic
analyzer.
01/2011
-
05/2012
Digital IC Design Consultant
Intel Mobile Communications
GmbH
IC-Design Group of Intel Mobile Communications(IMC) in Dresden is
specialized in designing ICs for mobile communication. I worked on design
and verification of several blocks of an LTE-Baseband chip.
IC-Design Group of Intel Mobile Communications(IMC) in Dresden is
specialized in designing ICs for mobile communication. I worked on design
and verification of several blocks of an LTE-Baseband chip.
01/2011
-
05/2012
Consultant Digital IC Design
Intel Mobile Communications
Role: As a part of the IC-Design team I was involved in design and verification of
several LTE-Baseband chips. My activities involved RTL-coding for a given
DSP algorithm, functional verification, linting and trial synthesis.
Technologies: VHDL, ModelSim, Spyglass, Design Compiler, C, AMBA, Tensilica, DSP, FFT
several LTE-Baseband chips. My activities involved RTL-coding for a given
DSP algorithm, functional verification, linting and trial synthesis.
Technologies: VHDL, ModelSim, Spyglass, Design Compiler, C, AMBA, Tensilica, DSP, FFT
05/2008
-
01/2011
Corporate Application Engineer
Chipvision Design Systems AG
Role: As a Corporate Application Engineer at ChipVision Design Systems, I had
the responsibility to serve as an interface between customers and
engineering team. As a part of my responsibility, I processed the
customers' C++/SystemC code to perform high-level-synthesis with
PowerOpt and verified the correctness of the generated RTL-Verilog by
simulation.
the responsibility to serve as an interface between customers and
engineering team. As a part of my responsibility, I processed the
customers' C++/SystemC code to perform high-level-synthesis with
PowerOpt and verified the correctness of the generated RTL-Verilog by
simulation.
07/2005
-
01/2011
Corporate Application Engineer/ Senior Software Development Engineer
Chipvision Design Systems AG
at Chipvision Design Systems AG
Chipvision Design Systems is an EDA(Electronic Design Automation)
company, which has specialized in low-power high-level-synthesis. As
Senior Software Developer I contributed towards development of this
future oriented technology and as Corporate Application Engineer I
contributed towards effective application of this technology.
Chipvision Design Systems is an EDA(Electronic Design Automation)
company, which has specialized in low-power high-level-synthesis. As
Senior Software Developer I contributed towards development of this
future oriented technology and as Corporate Application Engineer I
contributed towards effective application of this technology.
05/2007
-
04/2008
Senior Software Development Engineer
Project: Programming of a Verilog-Writers
Role: ChipVision's high-level-synthesis tool PowerOpt outputs the RTL in Verilog.
Special attention is given on the readability of the generated code. As a
part of my work in the back-end group, I explored the forms of expression
in Verilog, which express the structure of the generated circuit in a more
readable fashion. Worked in a Scrum team to realize the Verilog-Writer.
Technologies: C++, Verilog, Icarus, Cadence RTL-Compiler (RC), Eclipse, Scrum
Role: ChipVision's high-level-synthesis tool PowerOpt outputs the RTL in Verilog.
Special attention is given on the readability of the generated code. As a
part of my work in the back-end group, I explored the forms of expression
in Verilog, which express the structure of the generated circuit in a more
readable fashion. Worked in a Scrum team to realize the Verilog-Writer.
Technologies: C++, Verilog, Icarus, Cadence RTL-Compiler (RC), Eclipse, Scrum
01/2007
-
04/2007
EDA Development Engineer
Project: Requirements gathering for PowerOpt
Role: ChipVision decided to bring out a high-level-synthesis tool in the beginning
of 2007. Requirements gathering was obviously the the first step in the
huge project ahead. At that phase, I interacted with two groups: Synthesis
Kernel Group and Back-End-Group. I took part in brain storming sessions
to capture the requirements for the new Product PowerOpt.
Role: ChipVision decided to bring out a high-level-synthesis tool in the beginning
of 2007. Requirements gathering was obviously the the first step in the
huge project ahead. At that phase, I interacted with two groups: Synthesis
Kernel Group and Back-End-Group. I took part in brain storming sessions
to capture the requirements for the new Product PowerOpt.
07/2005
-
12/2006
EDA Development Engineer
Project: LEMOS - Low-Power Design Methods for Mobile Systems
Mobile systems have special requirements on low power design methods.
In this project, new methods for estimation and optimization of
dissipation losses in the mobile systems were explored.
Role:
As a part of this research project, I analyzed clock trees, which are highly
critical networks with respect to dissipation losses. As a result of this
research, new methods for estimation and optimization of dissipation
losses were developed. I verified the developed models using Cadence's
SoC Encounter. I integrated the source-code in Chipvision's estimation
tool ORINOCO
Technologies:
Verilog, C++, QT Libraries, SoC-Encounter, NC-Sim, X-Graph, Eclipse
Mobile systems have special requirements on low power design methods.
In this project, new methods for estimation and optimization of
dissipation losses in the mobile systems were explored.
Role:
As a part of this research project, I analyzed clock trees, which are highly
critical networks with respect to dissipation losses. As a result of this
research, new methods for estimation and optimization of dissipation
losses were developed. I verified the developed models using Cadence's
SoC Encounter. I integrated the source-code in Chipvision's estimation
tool ORINOCO
Technologies:
Verilog, C++, QT Libraries, SoC-Encounter, NC-Sim, X-Graph, Eclipse
08/2004
-
06/2005
System and Hardware Development Engineer
Hightronix GmbH
Project: OSIS Compliant Measuring Head
OSIS is an emerging standard for the electromechanical and software
interfaces of the measuring heads for coordinate measurement machines
(CMMs). The goal of the project was to integrate a higher resolution
image sensor (LUPA4000) in the design and thereby considering all
compliance guidelines from OSIS consortium.
Role: Digital highspeed hardware (FPGA based) and firmware development,
PCBDesign and layout, System Integration and testing.
Technologies: C++, VHDL, Quartus, Protel, Analog Electronics, MS-Project
06/2004-03/2005
Position: System and Hardware Development Engineer
Project: Dentascope with 2 synchronous optical 3D-Sensors
Dentascope is a compact and highly precise 3D Scanner, especially
designed for applications in the dental technology applications. For an
international customer, the existing Dentascope design had to be
modified to allow synchronous measurements with 2 sensors, in order to
achieve higher measuring speed. The work included integration of a new
1M-Pixel image sensor (IBIS5) in the design and the implementation of the
synchronicity between two arbitrary sensors for parallel measurements.
Role: Design coordinator and system architect. Shared responsibility for
Hardware and firmware development and integration and PCB designing.
Technologies: C++, VHDL, Quartus, , Altium Designer, NIOS, Ethernet, TCP/IP, I2C,
Analog Electronics, Logic Analyzer, Oscilloscope, MS-Project
OSIS is an emerging standard for the electromechanical and software
interfaces of the measuring heads for coordinate measurement machines
(CMMs). The goal of the project was to integrate a higher resolution
image sensor (LUPA4000) in the design and thereby considering all
compliance guidelines from OSIS consortium.
Role: Digital highspeed hardware (FPGA based) and firmware development,
PCBDesign and layout, System Integration and testing.
Technologies: C++, VHDL, Quartus, Protel, Analog Electronics, MS-Project
06/2004-03/2005
Position: System and Hardware Development Engineer
Project: Dentascope with 2 synchronous optical 3D-Sensors
Dentascope is a compact and highly precise 3D Scanner, especially
designed for applications in the dental technology applications. For an
international customer, the existing Dentascope design had to be
modified to allow synchronous measurements with 2 sensors, in order to
achieve higher measuring speed. The work included integration of a new
1M-Pixel image sensor (IBIS5) in the design and the implementation of the
synchronicity between two arbitrary sensors for parallel measurements.
Role: Design coordinator and system architect. Shared responsibility for
Hardware and firmware development and integration and PCB designing.
Technologies: C++, VHDL, Quartus, , Altium Designer, NIOS, Ethernet, TCP/IP, I2C,
Analog Electronics, Logic Analyzer, Oscilloscope, MS-Project
01/2004
-
06/2005
System and Hardware Development Engineer
Hightronix GmbH
The company was a leading supplier of highly precise optical sensors for
coordinate measurement machines. As a System and Hardware
Development Engineer, I developed the concepts, realized them in
Hardware and Software and tested and debugged the products until their
production maturity
coordinate measurement machines. As a System and Hardware
Development Engineer, I developed the concepts, realized them in
Hardware and Software and tested and debugged the products until their
production maturity
01/2004
-
06/2004
System and Hardware Development Engineer
Project: Prototype 3D-Scanner with embedded TCP/IP Interface
The existing measuring head, which had most of its electronics placed on
an ISA-Bus based card, had to be decoupled from the host computer and
the whole electronics had to be placed in the measuring head itself and
the communication between the measuring head and the host computer
had to be realized by TCP/IP interface. Here I had the opportunity to
architecture a whole new system.
Role: Lead-Designer and system architect. I developed the system on the basis
of Altera's softcore processor NIOS. As embedded TCP/IP-solution I
decided to take a hard-wired TCP/IP controller from the Korean company
Wiznet and I wrote a driver of this component to run on NIOS. As a
prototype, I developed the whole design as a piggy-back PCB on Altera's
Apex evaluation board.
Technologies: C++, VHDL, Quartus, SoPC Builder, NIOS, Ethernet, TCP/IP, Analog
Electronics, Logic Analyzer, Oscilloscope, several other lab instruments.
The existing measuring head, which had most of its electronics placed on
an ISA-Bus based card, had to be decoupled from the host computer and
the whole electronics had to be placed in the measuring head itself and
the communication between the measuring head and the host computer
had to be realized by TCP/IP interface. Here I had the opportunity to
architecture a whole new system.
Role: Lead-Designer and system architect. I developed the system on the basis
of Altera's softcore processor NIOS. As embedded TCP/IP-solution I
decided to take a hard-wired TCP/IP controller from the Korean company
Wiznet and I wrote a driver of this component to run on NIOS. As a
prototype, I developed the whole design as a piggy-back PCB on Altera's
Apex evaluation board.
Technologies: C++, VHDL, Quartus, SoPC Builder, NIOS, Ethernet, TCP/IP, Analog
Electronics, Logic Analyzer, Oscilloscope, several other lab instruments.
10/2003
-
12/2003
ASIC Design Engineer
Agere Systems
Project: SDH/SONET Network Processor
This ASIC component was designed by Munich Design-Center team on
behalf of a renowned international customer. The design was very timing
critical, since this component supports bit-rates of 2.5G and 10G. This chip
was to be fabricated with 130 nm process.
Role: Worked on timing closure of some parts of the design. I integrated SERDES
macro (Serializer/Deserializer) in the design and I generated test-vectors in
order to test SERDES and PRBS macros.
Technologies: Astro, RC-Extract, Assura, Prime Time, NC-Verilog, Formality, TCL, Perl
This ASIC component was designed by Munich Design-Center team on
behalf of a renowned international customer. The design was very timing
critical, since this component supports bit-rates of 2.5G and 10G. This chip
was to be fabricated with 130 nm process.
Role: Worked on timing closure of some parts of the design. I integrated SERDES
macro (Serializer/Deserializer) in the design and I generated test-vectors in
order to test SERDES and PRBS macros.
Technologies: Astro, RC-Extract, Assura, Prime Time, NC-Verilog, Formality, TCL, Perl
04/2001
-
12/2003
ASIC Design Engineer
Lucent/Agere System, Munich-Design-Center
Worked mainly in Back-End designing (Timing-driven Layout, Floor-
Planning, Static Timing Analysis, Design for Testability, functional and
timing simulations, SPICE simulations of high frequency digital circuits.)
Planning, Static Timing Analysis, Design for Testability, functional and
timing simulations, SPICE simulations of high frequency digital circuits.)
06/2002
-
09/2003
ASIC Design Engineer
Project: SDH/SONET Network Termination Device (TADM2)
TADM2 was a redesign of Agere System's TADM chip, which realizes a
highly integrated Network termination device for ring and linear networks
with flexible payload mapping. Bad test coverage was one of the main
reasons for the redesign of TADM.
Role: I worked on the improvement of test coverage. One of the reasons of the
bad test coverage were unfixed hold-time violations, which were corrected
by the colleagues by introducing lock-up latches. With this improved design
and by using newest ATPG algorithms I could significantly improve the test
coverage of the device.
Technologies: TETRAMAX, Design Compiler, NC-Verilog, formality, TCL, Perl
TADM2 was a redesign of Agere System's TADM chip, which realizes a
highly integrated Network termination device for ring and linear networks
with flexible payload mapping. Bad test coverage was one of the main
reasons for the redesign of TADM.
Role: I worked on the improvement of test coverage. One of the reasons of the
bad test coverage were unfixed hold-time violations, which were corrected
by the colleagues by introducing lock-up latches. With this improved design
and by using newest ATPG algorithms I could significantly improve the test
coverage of the device.
Technologies: TETRAMAX, Design Compiler, NC-Verilog, formality, TCL, Perl
06/2001
-
05/2002
ASIC Design Engineer
Project: PDH-Mapper ASIC
This mapper ASIC was designed on behalf of a big international concern.
The component can process 24 STS-1 or DS3 channels in parallel. Die
circuit was realized with 0.16 μm process.
Role: Worked on timing closure of some high frequency blocks of the design.
Further I defined pin out of the device on the basis of the toplevel-floorplan
and conducted package verification using OPUS/NEXUS tools. Worked
closely with test engineer and provided test vectors.
Technologies: Jupiter, NC-Verilog, formality, IKOS, HSPICE, OPUS, NEXUS, Perl, scripting
This mapper ASIC was designed on behalf of a big international concern.
The component can process 24 STS-1 or DS3 channels in parallel. Die
circuit was realized with 0.16 μm process.
Role: Worked on timing closure of some high frequency blocks of the design.
Further I defined pin out of the device on the basis of the toplevel-floorplan
and conducted package verification using OPUS/NEXUS tools. Worked
closely with test engineer and provided test vectors.
Technologies: Jupiter, NC-Verilog, formality, IKOS, HSPICE, OPUS, NEXUS, Perl, scripting
06/2001
-
05/2002
ASIC Design Engineer
Project: Line-ASIC
Line-ASIC project was canceled by the customers. Following tasks were
accomplished by me in the Quotation phase.
Role: Programming of a Verilog test-bench for a parameterized dual-clock FIFO
from the Synopsys Design-Ware Components. Due to the big bit width
requirement, the FIFO was realized by a combination of two FIFOs of half
bit width.
Technologies: Synopsys DesignWare, Design Compiler, Verilog, NC-Verilog.
Line-ASIC project was canceled by the customers. Following tasks were
accomplished by me in the Quotation phase.
Role: Programming of a Verilog test-bench for a parameterized dual-clock FIFO
from the Synopsys Design-Ware Components. Due to the big bit width
requirement, the FIFO was realized by a combination of two FIFOs of half
bit width.
Technologies: Synopsys DesignWare, Design Compiler, Verilog, NC-Verilog.
03/2000
-
03/2001
Student employee
Chair of process and aerosol measurement technology, University of Duisburg-Essen
technology, University of Duisburg-Essen. I worked on the development of
a CAN-Bus Network of measurement nodes for the synchronous
measurements. I did my master's thesis in the same institute on the topic
"CAN-Network of peripheral sensors of an optical particle counter". For the
development, I used CAN-Controller of Microchip and PIC microcontroller.
a CAN-Bus Network of measurement nodes for the synchronous
measurements. I did my master's thesis in the same institute on the topic
"CAN-Network of peripheral sensors of an optical particle counter". For the
development, I used CAN-Controller of Microchip and PIC microcontroller.
12/1998
-
06/1999
driver software
Infineon Technologies development center
06/1997
-
04/1998
student employee
Chair of Automation Technology
Ruhr-University Bochum. I worked as a C++ Programmer on the
development of an image processing system for contactless geometry
acquisition.
development of an image processing system for contactless geometry
acquisition.
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