Beschreibung
We are looking for a
Digital Verification Engineer (m/f)
Reference: -en
Start: asap
Duration: 3 MM
Place: in Styria
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- Create module level verification for a key block in the design
- Create and maintain module level verification environment
- Write test-cases
- Create assertions, checkers and coverage reusable for top-level verification
- Sign off the functionality of the block
- Integration testing on top-level
- Map checkers to vplan
Your qualifications
- Solid knowledge of SystemVerilog
- Practical knowledge of SystemVerilog assertions
- Detailed experienced in verification planning using Cadence vplanner
- Basic knowledge of regulation loops is a plus
Skills:
- Hardware developer
Keywords: digital verification engineer Hardwareentwickler