Beschreibung
My Client base in Austria are looking for an Analog / RF Layout engineer (physical design engineer) for intially a six month assignment.The ideal enfgineer should have 5-10 years experience in CMOS technology (140nm and/or below) with a good understanding about RF design/ABCD technology (high voltage) , Matching structures.
The engineer will be working in the following tecnologies: Cadence virtuoso 6.1.6, Cadence PVS, Cadence Quartus/Assura/QRC
If this sounds of interest then don't delay and send me your CV today.